1. Field of the Invention
The present invention relates to a semiconductor device in which an n-channel MIS transistor and a p-channel MIS transistor are formed on the same substrate, and a manufacturing method thereof.
2. Description of the Related Art
An improvement in performance of a CMOS circuit has been achieved by miniaturization of an MISFET based on a scaling law. However, in the present day, a gate length is 50 nm or below, which raises various problems due to miniaturization. Therefore, in order to further improve the performance of a CMOS circuit, a technology of increasing a mobility of a channel as well as miniaturization is required. As means for increasing the mobility, a method of applying a strain to a channel, a method of using a plane orientation different from a regular (100) surface, or a method of using SiGe or Ge as a high-mobility material for a channel has been proposed.
On the other hand, suppression of an short channel effect is the most important problem in an extremely scaled MISFET, and a multi-gate MISFET superior in immunity of short channel effects has attracted attention in recent years. In the multi-gate MISFET, since a controlling power of a gate is increased as compared with a conventional planar MISFET, the short channel effect is suppressed. Therefore, it can be considered that appropriate integration of the mobility enhancement technologies and these multi-gate MISFETs is important to realize a lower power consumption/high-performance CMOS in the future.
However, in order to obtain a high mobility for both an nMISFET and a pMISFET in a CMOS structure using the multi-gate MISFET, it has been conventionally considered that current directions must be changed depending on the nMISFET and the pMISFET (see, e.g., JP-A 2001-160594 (KOKAI)). That is, in the case of using a regular (001) substrate, a Fin side surface is a (100) surface when a current direction is a <100> direction, and the Fin side surface is a (110) surface when the current direction is a <110> direction. On the other hand, mobilities of electrons and holes vary depending on respective surfaces, and the mobility of electrons has a relationship of (100)>(110), and the mobility of holes has a relationship of (100)<(110). Therefore, the current direction must be set to the <100> direction in the nMISFET, and the current direction must be set to the <110> direction in the pMISFET. In order to set such current directions, a device direction of the nMISFET must be inclined 45° with respect to a device direction of the pMISFET, and there is a problem of an area penalty or complication of a circuit design.
Further, although using a single semiconductor layer as a material is desirable for fabrication of the multi-gate MISFET in terms of a scalability of the Fin, a method of using the single semiconductor layer to uniformly apply a tensile strain to the nMISFET in the current direction and a compressive strain to the pMISFET in the current direction has not been realized yet.
As explained above, it has been conventionally considered that device directions of the nMISFET and the pMISFET must be inclined by 45°, the Fin side surface must be set as a (100) surface in the nMISFET, and the Fin side surface must be set as a (110) surface in the pMISFET in order to optimize plane orientations and strains in both the nMISFET and the pMISFET in the multi-gate CMOS structure. However, this structure has a problem of an area penalty or complication of a circuit design. Furthermore, using a single semiconductor layer to uniformly apply an optimum strain to each of the nMISFET and the pMISFET is difficult.
Therefore, realization of a semiconductor device having the multi-gate CMOS structure that can improve a mobility of each device without inclining device directions in the nMISFET and the pMISFET and a manufacturing method thereof is demanded.